`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:32:41 03/31/2022
// Design Name:   openmips_min_sopc
// Module Name:   E:/OpenMIPS/openmips_min_sopc_tb.v
// Project Name:  OpenMIPS
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: openmips_min_sopc
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
`include "define.v"
module openmips_min_sopc_tb;

	// Inputs
	reg clk;
	reg rst;

	// Instantiate the Unit Under Test (UUT)
	openmips_min_sopc uut (
		.clk(clk), 
		.rst(rst)
	);

	initial begin
		// Initialize Inputs
		clk = 1'b0;

		forever #10 clk=~clk;

	end
	
	initial begin
		rst=`RstEnable;
		#195 rst=`RstDisable;
	end
      
endmodule

